Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Another goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flipchip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flipchip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on metal contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flipchip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
FIG. 1 illustrates a portion of flipchip 10 with a bump 12 formed on metal contact pad 14. The bump 12 is then metallurgically and electrically connected to metal contact pad 15 on substrate 16 using a bump reflow process. To connect bump 12 and contact pad 15, a solder resist or mask opening 18 is disposed over a surface of the substrate to confine the bump reflow to the physical boundaries of contact pad 15, see FIG. 2a. Due to manufacturing alignment tolerances as to the relative position between contact pad 15 and solder resist opening 18, contact pad 15 is made substantially larger than solder resist opening 18 to ensure that the full metal area of the contact pad is exposed, given the alignment tolerance of the solder resist opening. In generally, the minimum size of contact pad 15 is Pmin=SRO+2*SRR, where SRO is the minimum solder resist opening required to ensure good metallurgical connection and SRR is the solder resist alignment tolerance, also known as solder registration. In one example, if solder resist opening 18 is 90 microns and the solder resist alignment tolerance is 25 microns, then, according to the known design rule, contact pad 15 is made 140 microns in diameter. Thus, under the known design rule, and given the maximum manufacturing alignment tolerance, the solder resist opening always falls within the contact pad and leaves no voids or empty space around the pad, as shown in FIG. 2b. 
Unfortunately, the larger contact pad required to ensure that the solder resist opening always falls within the full metal area of the contact pad limits the metal signal trace or track routing density that can be achieved on the substrate. The larger contact pad necessarily reduces trace routing density as fewer traces can be placed between the contact pads. In addition, the larger contact pad translates to fewer contacts pads per unit area of the substrate.